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| CXD3152R signal processor lsi for single-chip ccd b/w camera description the CXD3152R is a digital signal processor lsi for ccd black-and-white cameras. in addition to the cds and agc circuits of conventional analog signal processor lsi, this chip also features the ease of use and functions of digital signal processing. features supports 510h/760h system ccd image sensors supports eia/ccir modes built-in cds and agc circuits built-in 10-bit a/d converter analog and digital signal output right/left inverted (mirror image) output function horizontal and vertical aperture correction function gamma correction curve variable function serial communication function (i 2 c bus) supports external sync functions (when using the cxd2463r) ?line lock/vreset hpll supports backlight compensation functions (when using the cxd2463r) character input pin blemish detection and compensation function absolute maximum ratings supply voltage v dd (3.3v) v ss ?0.3 to +4.6 v v dd (5.0v) v ss ?0.3 to +6.0 v input voltage v i (3.3v) v ss ?0.3 to v dd 3 + 0.3 v v i (5.0v) v ss ?0.3 to v dd 5 + 0.3 v output voltage v o (3.3v) v ss ?0.3 to v dd 3 + 0.3 v v o (5.0v) v ss ?0.3 to v dd 5 + 0.3 v storage temperature tstg ?5 to +125 ? recommended operating conditions supply voltage v dd (3.3v) 3.0 to 3.6 v v dd (5.0v) 4.75 to 5.25 v applications various ccd black-and-white cameras applicable ccd image sensors ? 510h system ccds icx054bl/055bl (type 1/3 eia/ccir) icx254al/255al (type 1/3 eia/ccir) icx206al/207al (type 1/4 eia/ccir) icx226al/227al (type 1/4 eia/ccir) 760h system ccds icx038dla/039dla (type 1/2 eia/ccir) icx248al/249al (type 1/2 eia/ccir) icx058cl/059cl (type 1/3 eia/ccir) icx258al/259al (type 1/3 eia/ccir) icx208al/209al (type 1/4 eia/ccir) icx228al/229al (type 1/4 eia/ccir) supported related lsis tg : cxd2463r eeprom : s-24c01b (seiko instruments co., ltd.) or equivalent product ? applicable ccd image sensors are applicable products as of preparing this data sheet. they may be changed according to the version up and production stop of ccd image sensor. ?1 e00565-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin lqfp (plastic)
?2 CXD3152R cds amp agc controller 10bit adc dac agc clp clp amp register 9bit dac over sampling csync wc ped blk gain gamma y. gain gain sw 3h memory v. follower timing generator sync separator blemish detector hv ap. con blemish correction 54 27 10 8 7 6 64 5 2 55 59 39, 38 13, 14 15, 16 3, 4 58, 57 63, 62 60, 61, 25, 26 37, 33, 34 44 to 48, 50 to 52 41, 42, 40 ana, anab chara mirror refh, refl refhin, reflin monitor capb2 yin yout gout irisout ccdin shp shd 2mcki csync_in ccd, eia blcw1, 2 agc, dgc sda, scl, regres y0 to y7 pref, cvref, comp cap1, capa2 block diagram 3 CXD3152R description of functions by block cds & agc cds v dd 1 = 5.0v shd/shp external input: 4 CXD3152R d/a converter dac 9 bits v dd 6 = 3.3v supports 40 to +130 ire output timing generation timing generation of various dsp internal signal processing pulses input clock frequencies: eia (510 492) : 19.0699mhz ccir (500 582) : 18.9375mhz eia (768 494) : 28.63636mhz ccir (752 582) : 28.375mhz slave operation according to the sync signal 5 CXD3152R pin configuration 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd 1 (5v) ccdin cap1 capa2 irisout yout yin capb2 v ss 1 monitor v ss 2 v dd 2 (5v) refhin reflin refh refl y4 y3 y2 y1 y0 oeb scl sda regres ana anab rref v dd 6 (3.3v) v ss 6 comp cvref v ss 5 mckphs gamma2 gamma1 apcon mirror dgc agc v dd 5 (3.3v) defect test v ss 4 v dd 4 (3.3v) refbias v dd 3 (3.3v) v ss 3 v ss 7 y5 y6 y7 mcko chara 2mcki v dd 7 (3.3v) eia ccd csync_in blcw1 blcw2 shd shp gout 6 CXD3152R pin description pin no. symbol i/o description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v dd 1 ccdin cap1 capa2 irisout yout yin capb2 v ss 1 monitor v ss 2 v dd 2 refhin reflin refh refl v ss 3 v dd 3 refbias v dd 4 v ss 4 test defect v dd 5 agc dgc mirror apcon gamma1 gamma2 p i o(a) o(a) o(a) o(a) i(a) i(a) p o(a) p p i(a) i(a) o(a) o(a) p p o(a) p p i i p i i i i i i analog power supply (5.0v) image signal input from ccd cds dc bias output connect to gnd via an approximately 0.1f capacitor. gain control amplifier dc bias output connect to gnd via an approximately 0.1f capacitor. image signal output for iris detection agc image signal output image signal input to adc normally input yout via an approximately 0.01f capacitor. adc input clamp level (dc) input high reference (refhin) reference level analog gnd output for monitoring the signal input to adc analog gnd analog power supply (5.0v) adc high reference input adc low reference input adc high reference output connect to gnd via an approximately 0.1f capacitor. adc low reference output connect to gnd via an approximately 0.1f capacitor. analog gnd analog power supply (3.3v) adc dc bias output connect to gnd via an approximately 0.1f capacitor. digital power supply (3.3v) digital gnd test pin. normally fix high. blemish compensation function switching 0: off, 1: on digital power supply (3.3v) analog gain switching 0: fixed, 1: auto digital gain switching 0: fixed, 1: auto mirror inversion switching 0: standard, 1: mirror aperture correction switching 0: off, 1: on gamma correction characteristics switching 00: 0.45, 01: 0.6 (register setting), 10: 1.0, 11: s curve 7 CXD3152R pin no. symbol i/o description 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 62 mckphs v ss 5 cvref comp v ss 6 v dd 6 (3.3v) rref anab ana regres sda scl oeb y0 y1 y2 y3 y4 v ss 7 y5 y6 y7 mcko chara 2mcki v dd 7 eia ccd csync_in shd i p o(a) o(a) p p o(a) o(a) o(a) i ? i/o ? i/o ? i o o o o o p o o o o i ? i ? p i ? i ? i ? i ? 2mcki input polarity switching 0: through, 1: inverted digital gnd dac reference voltage output connect to gnd via 0.1f. dac phase compensation. connect to gnd via 0.1f. digital gnd digital power supply (3.3v) dac reference voltage generation normally connect to gnd via 3.3k ? . dac negative output. normally connect to gnd via 200 ? . dac positive output. normally connect to gnd via 200 ? . register reset. all registers reset to the default when low. i 2 c bus data line i 2 c bus clock line digital output (y0 to y7) control. 0: output, 1: hi-z digital signal output (lsb) digital signal output digital signal output digital signal output digital signal output digital gnd digital signal output digital signal output digital signal output (msb) y0 to y7 latch clock output character signal input reference clock input digital power supply (3.3v) tv mode switching 0: eia, 1: ccir ccd number of horizontal pixels switching 0: 510h system, 1: 760h system composite sync input backlight compensation window switching 00: full-screen photometry, 01: bottom photometry 10: center photometry, 11: bottom + center photometry data block sampling pulse input 60 61 i ? i ? blcw1 blcw2 8 CXD3152R pin no. symbol i/o description 63 64 shp gout i ? o(a) precharge block sampling pulse input agc gain control voltage output (dac output) connect to gnd via an approximately 0.1f capacitor. note 1) asterisks ( ? ) indicate that either 3.3v or 5.0v input is possible. note 2) the i/o column symbol meanings are as follows. i : digital input o : digital output i/o : digital input/output i(a) : analog input o(a) : analog output p : power supply/gnd 9 CXD3152R logic block electrical characteristics dc characteristics 3.3v block (v dd = 3.0 to 3.6v, v ss = 0v) note 1) the applicable pins correspond to the following symbols. ? 1 agc, apcon, blcw1, blcw2, ccd, chara, mckphs, csync_in, defect, dgc, eia, gamma1, gamma2, 2mcki, mirror, test, oeb (input) ? 2 regres ? 3 mcko, y0 to y7 (output) ? 4 scl, sda (i/o) note 2) the ana, anab, comp, cvref, refbias, refh, refl and rref pins are not included in the dc characteristics. note 1) the applicable pins correspond to the following symbols. ? 5 shd, shp (input) note 2) the cap1, capa2, capb2, ccdin, refhin, reflin, yin, gout, irisout, monitor and yout pins are not included in the dc characteristics. item input high level voltage input low level voltage input high level voltage input low level voltage output low level voltage output high level voltage output low level voltage input leak current output leak current symbol v ih v il v ih v il v ol v oh v ol i il i oz conditions cmos supported cmos schmitt supported i ol = 4ma i oh = 4ma i ol = 4ma v i = v dd , v ss at high impedance output min. 0.7v dd 0.75v dd v dd 0.8 10 10 typ. max. 0.2v dd 0.15v dd 0.4 0.4 +10 +10 unit v v v v v v v a a applicable pins ? 1 ? 2 , ? 4 ? 4 ? 3 ? 1 , ? 2 , ? 4 ? 3 , ? 4 item input high level voltage input low level voltage input leak current symbol v ih v il i il conditions cmos supported v i = v dd , v ss min. 0.7v dd 10 typ. max. 0.3v dd +10 unit v v a applicable pins ? 5 ? 5 5.0v block (v dd = 4.75 to 5.25v, v ss = 0v) 10 CXD3152R ac characteristics (output load: c l = 50pf) item csync_in fall setup time, activated by the falling edge of 2mcki csync_in fall hold time, activated by the falling edge of 2mcki delay time from the falling edge of 2mcki to mcko output csync_in fall setup time, activated by the rising edge of 2mcki csync_in fall hold time, activated by the rising edge of 2mcki delay time from the rising edge of 2mcki to mcko output chara setup time, activated by the falling edge of mcko chara hold time, activated by the falling edge of mcko delay time from the falling edge of mcko to y0 to y7 output power-on reset time reset pulse width scl clock frequency scl clock high level width scl clock low level width sda setup time, activated by the rising edge of scl sda hold time, activated by the falling edge of scl delay time from the falling edge of scl to sda low level output delay time from the falling edge of scl to sda output floating shp rise time, activated by the falling edge of 2mcki shd rise time, activated by the falling edge of 2mcki symbol t su1 t hd1 t dly1 t su2 t hd2 t dly2 t su3 t hd3 t dly3 t por t rst fscl t high t low t su4 t hd4 t dly4 t dly5 t dly6 t dly7 min. 10 10 10 10 0 20 1 1 700 700 30 0 0 typ. max. 20 20 15 500 20 15 30 unit ns ns ns ns ns ns ns ns ns s s khz ns ns ns ns ns ns ns ns 11 CXD3152R master clock generation timing (1) mckphs = low (2) mckphs = high thd1 2mcki csync_in mcko tsu1 tdly1 tdly1 tdly1 thd2 2mcki csync_in mcko tsu2 tdly2 tdly2 tdly2 video signal related input/output timing mcko chara y0 to y7 thd3 tsu3 tdly3 12 CXD3152R reset timing 3v tpor v dd regres trst v ih i 2 c bus timing scl sda (output) sda (input) thigh tsu4 hi-z thd4 tdly4 tdly5 tlow analog signal processing sampling pulse timing tdly6 tdly7 2mcki shp shd adclk tdly8 tdly8 note 1) when mckphs = low 13 CXD3152R analog block electrical characteristics 10-bit a/d converter electrical characteristics (v dd 3 = 3.3v, v ss = 0v, ta = 25 c) item symbol min. typ. max. unit test conditions dc accuracy dc accuracy resolution conversion frequency nonlinearity error differential nonlinearity error res fs i.l. d.l. 15 10 20 2.0 1.0 bits msps lsb lsb item symbol min. typ. max. unit test conditions dc accuracy dc accuracy resolution conversion frequency zero scale output voltage full scale output voltage full scale output current nonlinearity error differential nonlinearity error res fs v zero v full i full i.l. d.l. 15 1.21 0 0 1.30 6.6 10 20.0 15 1.43 16.5 2.0 1.0 bits msps mw v ma lsb lsb ? for the test circuit conditions, refer to the analog characteristics test circuit. ? for the power supply names, refer to the symbols in the pin description. 9-bit d/a converter electrical characteristics (v dd 6 = 3.3v, v ss = 0v, ta = 25 c) ? for the test circuit conditions, refer to the analog characteristics test circuit. ? for the power supply names, refer to the symbols in the pin description. 14 CXD3152R cds-agc electrical characteristics (v dd 1, 2 = 5.0v, v dd 3 = 3.3v, v ss = 0v, ta = 25 c) item symbol min. typ. max. unit test conditions cap1 output dc level ccdin = 1.6v (dc) gout = 1.5v capa2 output dc level ccdin = 1.6v (dc) gout = 1.5v yout output dc level ccdin = 1.6v (dc) gout = 2.5v gcof1 = v4 cdsdc v4 = yout output dc level ccdin = 1.6v (dc) gout = 1.5v gcof2 = v5 cdsdc v5 = yout output dc level ccdin = 1.6v (dc) gout = 0.5v yout output gain ccdin = s1 (note 2) gout = 3.3v yout output gain ccdin = s1 (note 2) gout = 0v yout output ac level ccdin = s1 (note 3) gout = 0.5v yout output ac level ccdin = s1 (note 3) gout = 2.5v irisout dc level ccdin = 1.6v (dc) gout = 3.3v irisout gain ccdin = s2 (note 4) gout = 3.3v irisout ac level ccdin = s2 (note 5) gout = 3.3v cap1 dc level capa2 dc level cds dc level agc dc offset 1 agc dc offset 2 agc minimum gain characteristics (note 1) agc maximum gain characteristics (note 1) agc d range 1 agc d range 2 iris dc level iris gain iris d range cap1 capa2 cdsdc gcof1 gcof2 agcg1 agcg2 agcd1 agcd2 irisdc irisg irisdr 1.5 2.5 2.9 0.2 0.4 3.3 15.7 1.9 1.6 1.6 8.3 1.6 1.6 3.0 3.4 0 0 6.4 18.8 2.2 2.0 2.2 9.5 2.1 1.7 3.5 3.9 0.2 0.4 8.7 21.1 2.7 2.7 2.6 10.7 2.7 v v v mv mv db db v v v db v ? for the test circuit conditions, refer to the analog characteristics test circuit. ? for the power supply names, refer to the symbols in the pin description. note 1) refer to the agc gain characteristics. note 2) s1: va = 100 to 400mv, vb = 1.6v (va = peak to peak, vb = peak to gnd) note 3) s1: va = 1000mv, vb = 1.6v note 4) s2: va = 400mv, vb = 1.6v note 5) s2: va = 1000mv, vb = 1.6v 15 CXD3152R clp electrical characteristics (v dd 1, 2 = 5.0v, v dd 3 = 3.3v, v ss = 0v, ta = 25 c) item symbol min. typ. max. unit test conditions capb2 output dc level sw1 = a, sw2 = a monitor output dc level clp = "h" sw1 = a, sw2 = a monitor output gain sw1 = b, sw2 = b yin = s4 (note 1) monitor output ac level sw1 = b, sw2 = a yin = s3 (note 2) capb2 dc level clp dc level clp gain clp d range capb2 clpdc1 clpg clpd 2.6 2.6 0 2.0 2.7 2.7 0.6 2.4 2.8 2.8 1.2 2.7 v v db v ? for the test circuit conditions, refer to the analog characteristics test circuit. ? for the power supply names, refer to the symbols in the pin description. note 1) s4: va = 1000mv, vb = 2.75v (va = peak to peak, vb = peak to gnd) note 2) s3: va = 2000mv, vb = 3.6v opamp electrical characteristics (v dd 1, 2 = 5.0v, v dd 3 = 3.3v, v ss = 0v, ta = 25 c) item symbol min. typ. max. unit test conditions refh output dc level sw1 = a, sw2 = a refl output dc level sw1 = a, sw2 = a opamp dc h opamp dc l oph opl 2.8 0.8 2.9 0.9 3.0 1.0 v v ? for the test circuit conditions, refer to the analog characteristics test circuit. ? for the power supply names, refer to the symbols in the pin description. agc gain characteristics (v dd 1, 2 = 5.0v, v dd 3 = 3.3v, v ss = 0v, ta = 25 c) 25 20 15 10 agc gain [db] 5 0 0 0.5 1.0 1.5 2.0 gout voltage [v] 2.5 3.0 3.3 agc gain characteristics 16 CXD3152R analog characteristics test circuit v v v v 0.1 f cap1 irisout capb2 chara refbias gout capa2 test adclk comp cvref clk apcon 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 200 ? 3.2k ? 0.1 f 0.1 f 0.1 f 0.1 f 0.825v 2.925v sw2 sw1 0.1 f a b b a 200 ? cds shd shp ccdin shd shp dgc yout defect refhin reflin rref anab ana gamma1 mcko y7 to y0 refh refl agc monitor yin clp clp 10-bit adc 9-bit dac test amp agc 17 CXD3152R analog input/output pin equivalent circuits pin no. 5 symbol irisout i/o o 6 yout o 10 2 13 14 7 monitor ccdin refhin reflin yin o i i i i equivalent circuit description video signal output pin for iris detection maximum output amplitude = 2.10vp-p (typ.) video signal output pin of gain control amplifier (agc) maximum output amplitude = 2.25vp-p (typ.) black level = 3.40v dc (typ.) video signal output of analog clamp circuit monitor pin for input signal to adc black level = 2.75v dc (typ.) maximum input amplitude = 3.40vp-p (maximum video signal amplitude from precharge level = 2.00vp-p) dc input bias = 1.80 0.1v high reference input pin for adc 2.92v dc input (typ.) low reference input pin for adc 0.82v dc input (typ.) input pin for video signal to undergo a/d conversion maximum input amplitude = 2.30vp-p (typ.) black level = 2.73v dc (typ.) v dd 1, 2 5 6 10 v dd 1, 2 13 2 14 v dd 1, 2 7 4 capa2 o dc bias output pin of the gain control amplifier 3.00v dc output (typ.) v dd 1, 2 10k 10k 1k 4 3 cap1 o dc bias output pin of the cds circuit 1.58v dc output (typ.) 8 capb2 o clamp level (dc) output pin of the clamp circuit for a/d conversion 2.73v dc output (typ.) v dd 1, 2 3 8 18 CXD3152R 64 gout o 15 16 refh refl o o gain control signal (8-bit dac for gain control) output pin for agc high reference output pin for adc voltage follower output 2.90v dc output (typ.) low reference output pin for adc voltage follower output 0.80v dc output (typ.) v dd 1, 2 v dd 7 1.5k 64 v dd 7 15 v dd 3 16 19 refbias o dc bias output pin for adc 1.55v dc output (typ.) v dd 3 19 38 anab o d/a converter negative output 0 to 1.24v output 39 ana o d/a converter positive output 0 to 1.24v output v dd 6 38 39 pin no. symbol i/o equivalent circuit description 19 CXD3152R 37 rref o 33 34 cvref comp o o dac reference voltage generation pin 1.32v dc output (typ.) dac reference voltage output pin 1.32v dc output (typ.) dac phase compensation pin 2.18v dc output (typ.) v dd 6 37 v dd 6 33 v dd 6 34 note) for the power supply names in the equivalent circuits, refer to the symbols in the pin description. pin no. symbol i/o equivalent circuit description 20 CXD3152R timing chart horizontal direction timing 2mck: master clock input for the CXD3152R mck: internal reference clock produced by dividing the input reference clock (2mck) in half. mcko: latch clock for digital output signal (inverted mck signal) ccdin: imaging signal from ccd shp: precharge level sampling pulse input shd: video level sampling pulse input cblk: internal composite blanking pulse (for video output signal) csync: composite sync pulse input (in phase for csync_in and the video output signal) a_clp: internal pulse for analog clamp d_clp: internal pulse for digital clamp dout[7:0]: 8-bit digital output signal ana: analog output signal vertical direction timing hd: internal horizontal sync signal cblk: internal composite blanking pulse (for video output signal) csync: composite sync pulse input (in phase for csync_in and the video output signal) a_clp: internal pulse for analog clamp d_clp: internal pulse for digital clamp ccdin: video signal from the ccd dout[7:0]: 8-bit digital output signal 21 CXD3152R horizontal direction timing chart eia 510h system count clk = 606f h = 19.0699/2mhz 2 6 11 16 19 4 3 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 13 12 11 7 6 5 3 2 1 15 16 17 18 20 21 22 23 25 26 27 28 30 60 80 90 100 110 120 2mck shp mck ccdin 0 10 20 mcko d_clp shd csync a_clp cblk ana dout[7:0] 505 504 503 502 501 500 499 499 505 59 14 14 24 8 16 509 508 507 506 104 10 9 8 14 4 19 24 510 17.5 clocks 22 CXD3152R horizontal direction timing chart ccir 510h system count clk = 606f h = 18.9375/2mhz 2mck d_clp shp shd csync a_clp mck ccdin 0 cblk ana dout[7:0] 10 20 30 60 90 100 110 120 130 mcko 59 14 14 24 8 16 13 12 11 7 6 5 3 2 1 499 498 497 496 15 16 17 18 20 21 22 23 25 26 27 28 4 3 2 5 6 7 2 8 9 10 11 12 13 14 15 16 17 18 19 19 6 11 16 495 494 493 492 491 490 489 489 495 114 500 10 9 8 14 19 24 4 17.5 clocks 23 CXD3152R horizontal direction timing chart eia 760h system count clk = 910f h = 28.63636/2mhz 2mck d_clp shp shd csync a_clp mck ccdin cblk ana dout[7:0] mcko 767 766 765 764 7 11 16 21 24 758 764 9 8 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 764 763 762 761 760 759 758 0 10 20 30 40 90 140 150 160 170 22 12 11 10 9 15 16 17 19 20 7 21 22 6 5 4 2 1 24 25 26 27 29 30 31 32 154 768 13 12 8 14 18 23 3 28 15.5 clocks 24 CXD3152R horizontal direction timing chart ccir 760h system count clk = 908f h = 28.375/2mhz 0 10 20 30 40 90 150 160 170 180 2mck d_clp shp shd csync a_clp mck ccdin cblk ana dout[7:0] mcko 751 750 749 748 12 11 10 8 16 17 18 7 6 5 3 2 1 20 21 22 23 25 26 27 28 9 13 22 12 18 21 743 749 11 10 9 12 13 14 15 16 17 18 19 20 21 749 748 747 746 745 744 743 13 14 15 19 24 9 4 752 169 13.5 clocks 25 CXD3152R vertical direction timing chart eia 510h/760h system 30 (292) 25 (287) 260 (522) 15 hd cblk csync a_clp ccdin even field 4 2 262 (524) odd field 10 8 6 25 30 258 (520) 4 (266) 260 2 (264) 258 8 (270) 6 (268) 10 (272) 15 (277) odd field even field d_clp dout[7:0] ob ob ob ob ob ob ob o b o b ob ob ob ob ob 27 28 29 30 31 32 478 479 478 479 480 481 480 481 482 483 482 483 484 485 484 485 486 487 488 489 492 493 494 ob 476 477 474 475 1 2 3 4 3 4 5 6 7 8 7 8 9 10 9 10 11 12 11 12 13 14 13 14 15 16 15 16 17 18 17 18 19 20 19 20 21 22 21 22 23 24 25 26 27 28 23 24 25 26 28 29 2 3 4 5 6 7 6 7 8 9 8 9 10 11 10 11 12 13 12 13 14 15 14 15 16 17 16 17 18 19 18 19 20 21 20 21 22 23 22 23 24 25 26 27 24 25 ob o b 479 480 479 480 481 482 481 482 483 484 483 484 485 486 485 486 487 488 489 490 491 492 493 494 475 476 477 478 o b ob o b o b o b o b o b o b o b ob ob 2 3 4 5 o b 1 5 6 2h 1 2 486 487 490 491 0 (262) 20 (282) 20 0 26 CXD3152R vertical direction timing chart ccir 510h/760h system 310 (622) 15 even field 4 2 0 312 (624) odd field 10 8 6 20 25 30 308 (620) 20 (333) 4 (317) 310 2 (315) 308 8 (321) 6 (319) 10 (323) 15 (328) odd field even field 30 (343) hd cblk csync a_clp ccdin dout[7:0] d_clp 577 578 581 582 ob o b 567 568 569 570 571 572 573 574 575 576 567 568 569 570 571 572 573 574 565 566 563 564 o b ob ob o b ob ob o b o b o b o b o b 16 17 578 579 580 581 576 577 582 ob ob 2 3 2 3 o b 1 4 5 6 7 6 7 8 9 8 9 10 11 10 11 12 13 12 13 14 15 14 15 568 569 568 569 570 571 570 571 572 573 572 573 574 575 574 575 566 567 564 565 o b o b ob ob ob ob ob ob o b o b ob ob 19 20 21 22 1 2 1 2 3 4 3 4 5 6 5 6 7 8 7 8 9 10 9 10 11 12 11 12 13 14 13 14 15 16 15 16 17 18 17 18 2h 575 576 579 580 ob 1 4 5 (313) 0 25 (338) 27 CXD3152R i 2 c serial communication 1. description of communication the CXD3152R performs serial communication between a pc or an external eeprom via the i 2 c bus. in communication with a pc, the pc is the master device and the CXD3152R is the slave device. on the other hand, in communication with an eeprom, the CXD3152R is the master device and the eeprom is the slave device. communication is performed using two signal lines: sda and scl. sda is a bidirectional serial data transfer line, and is used to transfer addresses from master to slave and to transfer data between master and slave. sda is normally pulled up to v dd by external resistance of several k ? . (therefore, sda is high at high impedance.) scl is a bidirectional serial clock transfer line, and is used as the data transfer synchronization clock. scl is driven by the master device, and like sda is pulled up to v dd by external resistance of several k ? . 2. slave address the CXD3152R i 2 c slave address is as follows. [a6:a0] = 0011111 (b) 3. i 2 c protocol communication conforms to the i 2 c bus protocol. data transfer is started when the bus is not in the busy status. during the data transfer period, the data line must be kept stable while the clock line is high. otherwise, data line changes while the clock line is high are interpreted as start or stop conditions. start condition the start condition occurs before all commands to the device, and is defined as sda changing from high to low when scl is high. stop condition the stop condition is defined as sda changing from low to high when scl is high. all operations must end in the stop condition. 4. communication timing during read, the sda data is taken in sync with the falling edge of scl. during write, the data is output to sda after a certain delay time from the falling edge of scl. the communication data is msb first. an overview of the byte-write and byte-read timings are described below. byte-write timing in the byte-write mode, the master device transmits the start condition and the slave address information (the r/w bit is set to 0) to the slave device. after the slave returns an acknowledgement, the master transmits the byte address to be written in the slave address pointer. after receiving the next acknowledgement from the slave, the master transfers the data to be written to the preceding address. the slave device returns an acknowledgement again, and the master generates the stop condition. slave address bus activity master sda line bus activity byte address data p s start ack ack ack stop 28 CXD3152R byte-read timing in the byte-read mode, the master device first transmits the start condition, the slave address, and the byte address of the position to be read to the slave device as a write operation. after the slave returns an acknowledgement, the master transmits the start condition and slave address (at this time the r/w bit is set to 1) again. after that, the slave issues an acknowledgement and transfers the read data. the master generates the stop condition without transmitting an acknowledgement. slave address slave address bus activity master sda line bus activity byte address data p ss start start ack ack ack no ack stop note 1) the upper 7 bits of the slave address indicate the device address, while the lowermost bit indicates the r/w mode. (read mode when this bit is high, and write mode when it is low.) note 2) the CXD3152R slave address is [a6:a0] = 0011111 (b). note 3) ack is the response acknowledgement signal, and the slave device goes to low. note 4) no ack means that a response acknowledgement signal is not returned. note 5) s: start condition, p: stop condition 29 CXD3152R description of registers address symbol regres wstart rstart ygam1 part symbol description r/w 00 (h) 0f (h) 10 (h) 14 (h) regres dummy wstart rstart ygam1 dummy w w w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default ff (h) ff (h) 00 (h) register reset 0: reset, 1: normal (the regres pin (pin 40) has precedence.) horizontal timing for write start to line memory set in mcki clock units 0x00 : earliest (advanced) position 0xfe : latest (delayed) position 0xff : internal fixed value eia510 system = 67 (h) ccir510 system = 71 (h) eia760 system = 95 (h) ccir760 system = a3 (h) horizontal timing for read start from line memory set in mcki clock units 0x00 : earliest (advanced) position 0xfe : latest (delayed) position 0xff : internal fixed value eia510 system = 5c (h) ccir510 system = 66 (h) eia760 system = 89 (h) ccir760 system = 96 (h) gamma correction curve adjustment-1 sets the intersection between the 1st approximation line (slope = 1) and the 2nd approximation line (slope = 3). setting range: 00 (h) to 1f (h) 30 CXD3152R address symbol ygam2 ygam3 ygam4 ygam5 part symbol description r/w 15 (h) 16 (h) 17 (h) 18 (h) ygam2 dummy ygam3 dummy ygam4 dummy ygam5 dummy w w w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 0a (h) 20 (h) 2e (h) 36 (h) gamma correction curve adjustment-2 sets the intersection between the 2nd approximation line (slope = 3) and the 3rd approximation line (slope = 3/2). setting range: 00 (h) to 3f (h) gamma correction curve adjustment-3 sets the intersection between the 3rd approximation line (slope = 3/2) and the 4th approximation line (slope = 1). setting range: 00 (h) to 7f (h) gamma correction curve adjustment-4 sets the intersection between the 4th approximation line (slope = 1) and the 5th approximation line (slope = 3/4). setting range: 00 (h) to 7f (h) gamma correction curve adjustment-5 sets the intersection between the 5th approximation line (slope = 3/4) and the 6th approximation line (slope = 1/2). setting range: 00 (h) to 7f (h) 31 CXD3152R address symbol ygam6 hapgain hapcore vapgain part symbol description r/w 19 (h) 1a (h) 1b (h) 1c (h) ygam6 dummy hapgain dummy hapcore1 hapcore2 vapgain dummy w w w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 41 (h) 09 (h) 02 (h) 00 (h) 04 (h) gamma correction curve adjustment-6 sets the intersection between the 6th approximation line (slope = 1/2) and the 7th approximation line (slope = 1/8). setting range: 00 (h) to 7f (h) the 7th approximation line is used for knee processing. horizontal aperture correction signal gain setting the gain changes linearly from 0 (h) to 7 (h). 0 (h): 0 f (h): maximum gain horizontal aperture correction signal noise suppression (coring) characteristics setting output = input hapcore1 if (output < 0), output = 0 00 (h): noise suppression off 3f (h): maximum noise suppression level horizontal aperture correction signal noise suppression (coring) characteristics setting output = input if (output hapcore2), output = 0 00 (h): noise suppression off 3f (h): maximum noise suppression level vertical aperture correction signal gain setting the gain changes linearly from 0 (h) to f (h). 0 (h): 0 f (h): maximum gain 32 CXD3152R address symbol vapcore apclip at_apcore ygain1 part symbol description r/w 1d (h) 1e (h) 1f (h) 20 (h) vapcore1 vapcore2 lclip hclip at_apcore dummy ygain1 dummy w w w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 02 (h) 00 (h) 04 (h) 06 (h) 1f (h) 3c (h) vertical aperture correction signal noise suppression (coring) characteristics setting output = input vapcore1 if (output < 0), output = 0 00 (h): noise suppression off 3f (h): maximum noise suppression level vertical aperture correction signal noise suppression (coring) characteristics setting output = input if (output vapcore2), output = 0 00 (h): noise suppression off 3f (h): maximum noise suppression level aperture correction signal minus side clip level setting output = input if (input lclip), output = lclip 0 (h): maximum clip level f (h): minimum clip level aperture correction signal plus side clip level setting output = input if (input hclip), output = hclip 0 (h): maximum clip level f (h): minimum clip level aperture correction signal coring level dgc link setting 0x0: coring off 0x1f: maximum coring level signal gain setting when gamma1 and gamma2 are set to 00 (gamma = 0.45) 33 CXD3152R address symbol ygain2 ygain3 ygain4 ped part symbol description r/w 21 (h) 22 (h) 23 (h) 24 (h) ygain2 dummy ygain3 dummy ygain4 dummy ped dummy w w w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 1f (h) 18 (h) 3a (h) 17 (h) signal gain setting when gamma1 and gamma2 are set to 10 (gamma = 0.6) signal gain setting when gamma1 and gamma2 are set to 01 (gamma = 1.0) signal gain setting when gamma1 and gamma2 are set to 11 (gamma = s) pedestal level setting the pedestal level changes linearly from 0 (h) to f (h). 00 (h): low 17 (h): 7.5 ire 3f (h): high 34 CXD3152R address symbol lowclip chara_g wt_clip bk_clip part symbol description r/w 25 (h) 27 (h) 28 (h) 29 (h) lclip dummy chara_g dummy wt_clip bk_clip dummy w w w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 00 (h) 32 (h) c4 (h) 1d (h) clip level setting for the black level and lower 0: 20 ire, 1: pedestal level externally input 1-bit character signal gain setting 00 (h): 85 ire 20 (h): 0 3f (h): +85 ire white clip level setting video signal minus component clip level setting 35 CXD3152R address symbol apgam1 apgam2 apsw agc_ref part symbol description r/w 2a (h) 2b (h) 2c (h) 32 (h) apgam1 dummy apgam2 dummy apsw dummy agc_ref dummy w w w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 3f (h) 7f (h) 01 (h) 18 (h) aperture signal gamma correction characteristics setting sets the intersection of the 1st approximation line (slope = 2) which passes through the origin and the 2nd approximation line (slope = 1). setting range: 00 (h) to 3f (h) aperture signal gamma correction characteristics setting sets the intersection of the 2nd approximation line (slope = 1) and the 3rd approximation line (slope = 1/2). setting range: 00 (h) to 7f (h) aperture correction signal added position setting 0: after gamma correction, 1: before gamma correction reference level setting for auto gain control integral value 36 CXD3152R address symbol dgcmin dgcmax agcmin agcmax part symbol description r/w 33 (h) 34 (h) 35 (h) 36 (h) dgcmin dgcmax agcmin dummy agcmax dummy w w w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 20 (h) a0 (h) 00 (h) 59 (h) digital gain control (dgc) minimum gain limiter setting valid when dgc = 1 when dgc = 0, this is the digital gain manual setting register. 20 (h) : 1.0 times (1f (h) and lower settings are prohibited) ff (h) : 8.0 times digital gain control (dgc) maximum gain limiter setting valid when dgc = 1 20 (h) : 1.0 times (1f (h) and lower settings are prohibited) 0xa0 : 5.0 times 0xff : 8.0 times analog gain control (agc) minimum gain limiter setting valid when agc = 1 when agc = 0, this is the analog gain manual setting register. 00 (h) : min 7f (h) : max analog gain control (agc) maximum gain limiter setting valid when agc = 1 00 (h) : min 7f (h) : max 37 CXD3152R address symbol agcwait agctm agchd max_n_def part symbol description r/w 37 (h) 38 (h) 39 (h) 4c (h) agcwait sw dummy agctm dummy agchd dummy max_n_def dummy w w w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 1d (h) 00 (h) 00 (h) 00 (h) 0a (h) auto gain control time constant setting hold time (hold_time) or feedback time (fb_time) can be selected by the sw setting. hold_time = (agcwait 2 + 2) vt vt: 1/60 (eia), 1/50 (ccir) (fb_time also uses the above formula.) hold time/feedback time selection 0: hold_time, 1: fb_time auto gain control feedback time setting 0: low speed, 1: high speed auto gain control hold setting 0: normal operation, 1: hold maximum number of registered blemishes setting maximum 10 points 38 CXD3152R address symbol defres def01 def02 def03 part symbol description r/w 5a (h) 64 (h) 65 (h) 66 (h) defres dummy x[0:7] x[8:9] y[0:5] y[6:8] d[0:4] w r/w r/w r/w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 01 (h) 00 (h) 00 (h) 00 (h) 00 (h) 00 (h) blemish detection operation reset 0: reset, 1: normal lower 8 bits of blemish pixel x address upper 2 bits of blemish pixel x address lower 6 bits of blemish pixel y address upper 3 bits of blemish pixel y address d0: even y address offset data relative to odd 0: offset value 0, 1: offset value 1 fixed to 1 d2: valid data/invalid data 0: invalid data, 1: valid data d3: internal data/external data 0: external, 1: internal dummy 39 CXD3152R address symbol def11 def12 def13 def21 def22 def23 def31 def32 def33 def41 def42 def43 def51 def52 def53 def61 def62 def63 def71 def72 def73 def81 def82 def83 def91 def92 def93 part symbol description r/w 67 (h) 68 (h) 69 (h) 6a (h) 6b (h) 6c (h) 6d (h) 6e (h) 6f (h) 70 (h) 71 (h) 72 (h) 73 (h) 74 (h) 75 (h) 76 (h) 77 (h) 78 (h) 79 (h) 7a (h) 7b (h) 7c (h) 7d (h) 7e (h) 7f (h) 80 (h) 81 (h) omitted: same as def01 omitted: same as def02 omitted: same as def03 omitted: same as def01 omitted: same as def02 omitted: same as def03 omitted: same as def01 omitted: same as def02 omitted: same as def03 omitted: same as def01 omitted: same as def02 omitted: same as def03 omitted: same as def01 omitted: same as def02 omitted: same as def03 omitted: same as def01 omitted: same as def02 omitted: same as def03 omitted: same as def01 omitted: same as def02 omitted: same as def03 omitted: same as def01 omitted: same as def02 omitted: same as def03 omitted: same as def01 omitted: same as def02 omitted: same as def03 bit default 40 CXD3152R address symbol adgc gamma blcw part symbol description r/w 96 (h) 97 (h) 98 (h) dgc agc sw dummy gam1 gam2 sw dummy blcw1 blcw2 sw dummy w w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 00 (h) 00 (h) 00 (h) 00 (h) 00 (h) 00 (h) 00 (h) digital gain switching (same function as dgc pin) 0: fixed, 1: auto analog gain switching (same function as agc pin) 0: fixed, 1: auto register setting/pin setting selection 0: pin setting, 1: register setting gamma correction characteristics switching (same function as gamma1 and gamma2 pins) 00: 0.45, 01: 0.6, 10: 1.0, 11: s curve register setting/pin setting selection 0: pin setting, 1: register setting backlight compensation window switching (same function as blcw1 and blcw2 pins) 00: full-screen photometry, 01: lower photometry 10: center photometry, 11: lower + center photometry register setting/pin setting selection 0: pin setting, 1: register setting 41 CXD3152R address symbol eia ccd mirror part symbol description r/w 99 (h) 9a (h) 9b (h) eia sw dummy ccd sw dummy mir sw dummy w w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 00 (h) 00 (h) 00 (h) 00 (h) 00 (h) 00 (h) tv mode switching (same function as eia pin) 0: eia, 1: ccir register setting/pin setting selection 0: pin setting, 1: register setting ccd number of horizontal pixels switching (same function as ccd pin) 0: 510h system, 1: 760h system register setting/pin setting selection 0: pin setting, 1: register setting mirror inversion switching (same function as mirror pin) 0: standard, 1: mirror register setting/pin setting selection 0: pin setting, 1: register setting 42 CXD3152R address symbol apcon ovsa defect dacsw part symbol description r/w 9c (h) 9d (h) 9e (h) 9f (h) apcon sw dummy dacsw dummy defect sw dummy dscsw dummy w w w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 00 (h) 00 (h) 01 (h) 00 (h) 00 (h) 00 (h) aperture correction switching (same function as apcon pin) 0: off, 1: on register setting/pin setting selection 0: pin setting, 1: register setting da conversion frequency setting 0: 2mcki/2, 1: 2mcki register setting/pin setting selection 0: pin setting, 1: register setting video output dac on/off 0: on, 1: off blemish compensation function switching (same function as defect pin) 0: off, 1: on 43 CXD3152R address symbol oeb chara part symbol description r/w a0 (h) a1 (h) oeb sw dummy chara sw dummy w w bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 default 00 (h) 00 (h) 00 (h) 00 (h) digital output (y0 to y7) switching (same function as oeb pin) 0: output, 1: hi-z register setting/pin setting selection 0: pin setting, 1: register setting 1-bit character signal input switching (same function as chara pin) register setting/pin setting selection 0: pin setting, 1: register setting 44 CXD3152R using the eeprom the CXD3152R can connect an external eeprom which supports the i 2 c bus. normally, read and write to and from the eeprom are performed from the pc master via the i 2 c bus to the slave eeprom. also, this ic can automatically read the user-set register values during power-on by writing the addresses and setting values for up to 64 registers in the eeprom. (at this time this ic is the master device and the eeprom is the slave device.) the serial eeprom s-24c01b made by seiko instruments co., ltd. or equivalent product can be used as the external eeprom. the external eeprom load timing during power-on or register reset is shown below for when an eeprom is mounted and not mounted. the i 2 c bus is occupied by the eeprom load at this period, so when using the i 2 c bus, other communication by the master device is prohibited for the following times from the rising edge of regress. regres scl/sda regres scl/sda when an eeprom is mounted when an eeprom is not mounted max. 135ms active (read from the eeprom) max. 2ms active (checking for eeprom presence) 45 CXD3152R package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 alloy package structure 64pin lqfp (plastic) 12.0 0.2 10.0 0.2 48 33 116 49 64 32 17 1.25 0.5 + 0.08 0.18 0.03 m 0.1 0.1 0.1 (0.5) 0.5 0.2 0 to 10 1.7 max detail a a 0.1 0.15 0.05 lqfp-64p-l061 lqfp064-p-1010-ay 0.3g sony corporation |
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